What Is Hdl Hardware Description Language

Hardware Description Languages

Hardware Description Languages

Sarah L. Harris , David Harris , in Digital Design and Computer Architecture, 2022

4.10 Summary

Hardware description languages (HDLs) are extremely important tools for modern digital designers. Once y'all have learned SystemVerilog or VHDL, you lot will exist able to specify digital systems much faster than if you had to draw the complete schematics. The debug cycle is also often much faster considering modifications require code changes instead of slow schematic rewiring. However, the debug cycle can exist much longer using HDLs if yous don't take a good idea of the hardware your lawmaking implies.

HDLs are used for both simulation and synthesis. Logic simulation is a powerful way to test a system on a computer earlier it is turned into hardware. Simulators let yous check the values of signals inside your arrangement that might be impossible to mensurate on a physical piece of hardware. Logic synthesis converts the HDL code into digital logic circuits.

The virtually of import thing to call up when you are writing HDL code is that you are describing real hardware, not writing a computer program. The most common beginner's fault is to write HDL code without thinking about the hardware you intend to produce. If yous don't know what hardware yous are implying, y'all are most certain non going to get what you want. Instead, brainstorm by sketching a block diagram of your arrangement, identifying which portions are combinational logic, which portions are sequential circuits or finite state machines, and so forth. Then, write HDL code for each portion, using the correct idioms to imply the kind of hardware yous need.

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Design Implementation

R.C. Cofer , Benjamin F. Harding , in Rapid System Prototyping with FPGAs, 2006

7.three.1 Dual Nature of HDL Languages

HDL languages tin be used for both design implementation and design simulation. Information technology is of import to empathise that certain HDL structures, and lawmaking constructs that tin can be used to simulate a design may not be able to exist translated into physical hardware. A consequence of the dual-nature of HDL languages is that a pattern described past "compilable" HDL lawmaking is non guaranteed to be synthesizable into a design that tin can be placed in a targeted FPGA. The designer must be aware of the specific structures and constructs that may exist used to generate hardware. Designers should also be able to implement the structures required for efficient design simulation. This is likely the greatest challenge associated with HDL-based design. Figure 7.7 illustrates the dual nature of VHDL and Verilog.

Effigy 7.7. HDL dual nature

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Introduction to Digital Logic Design with VHDL

Ian Grout , in Digital Systems Design with FPGAs and CPLDs, 2008

six.iii.3 HDL Pattern Entry

Hardware description language (HDL) blueprint entry is based on the creation and use of text-based descriptions of a digital logic circuit or system using a item HDL (the two IEEE standards in mutual use are Verilog^®-HDL and VHDL). Information technology is mutual to adopt a hierarchical design arroyo to keep a project manageable. The HDL code is written to adapt to one of three styles:

1.

A structural description describes the circuit construction in terms of the logic gates used and the interconnect wiring between the logic gates to course a circuit netlist.

2.

A dataflow clarification describes the transfer of data from input to output and between signals.

3.

A behavioral description describes the behavior of the design in terms of circuit or organization behavior using algorithms. This high-level description uses language constructs that resemble a high-level software programming language.

Both the dataflow and behavioral descriptions can use similar linguistic communication constructs. They differ in VHDL in that a behavioral description uses language process statements, whereas a dataflow description does not.

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Digital Building Blocks

Sarah L. Harris , David Coin Harris , in Digital Blueprint and Computer Architecture, 2016

Putting It All Together

This section introduced the half adder, full adder, and three types of carry propagate adders: ripple-carry, deport-lookahead, and prefix adders. Faster adders require more than hardware and therefore are more than expensive and ability-hungry. These trade-offs must be considered when choosing an appropriate adder for a blueprint.

Hardware description languages provide the+functioning to specify a CPA. Modern synthesis tools select among many possible implementations, choosing the cheapest (smallest) design that meets the speed requirements. This profoundly simplifies the designer's chore. HDL Example 5.i describes a CPA with carries in and out.

HDL Instance 5.1

Adder

SystemVerilog

module adder #(parameter North = 8)

(input   logic [Due north–ane:0] a, b,

  input   logic   cin,

  output logic [North–1:0] southward,

  output logic   cout);

assign {cout, south} = a + b + cin;

endmodule

VHDL

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

utilize IEEE.NUMERIC_STD_UNSIGNED.ALL;

entity adder is

  generic(N: integer := viii);

  port(a, b:   in   STD_LOGIC_VECTOR(N–1 downto 0);

  cin:   in   STD_LOGIC;

  s:   out STD_LOGIC_VECTOR(N–1 downto 0);

  cout:   out STD_LOGIC);

end;

architecture synth of adder is

  signal event: STD_LOGIC_VECTOR(N downto 0);

begin

  result <= ("0" & a) + ("0" & b) + cin;

  south   <= result(N–1 downto 0);

  cout   <= event(N);

end;

Figure 5.eight. Synthesized adder

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Pattern Languages

Ian Grout , in Digital Systems Design with FPGAs and CPLDs, 2008

four.3.2 VHDL

Very high-speed integrated circuit hardware description language—VHSIC HDL or VHDL—began life in 1980 nether a United states of america Section of Defense (DoD) requirement for the design of digital circuits following a common design methodology, providing the ability for self-documentation and re-use with new technologies. VHDL evolution commenced in 1983, and the language became an IEEE standard in 1987 (IEEE Std 1076-1987). The language was revised in 1993, 2000, and 2002, the latest release being 1076-2002. VHDL also has a number of associated standards relating to modeling and synthesis.

The HDL code is independent in an ASCII text file and therefore is transportable between EDA tools on the same computing system, between computers, betwixt unlike versions of the EDA tools and between the dissimilar engineers within the particular blueprint team.

The HDL code is written to adjust to i of three styles:

ane.

A structural clarification describes the circuit structure in terms of the logic gates used and the interconnect wiring betwixt the logic gates to form a circuit netlist.

2.

A dataflow description describes the transfer of data from input to output and betwixt signals.

3.

A behavioral description describes the behavior of the design in terms of the excursion and system behavior using algorithms. This high-level description uses language constructs that resemble a loftier-level software programming language.

Both the dataflow description and behavioral clarification apply like linguistic communication constructs, but in VHDL they differ: a behavioral description uses the language process statements, whereas a dataflow description does not.

In VHDL, a design is created initially as an entity announcement and an architecture body. The entity declaration describes the pattern I/O and includes parameters that customize the entity. The entity can be thought of as a black box with visible I/O connections. The architecture body describes the internal working of the entity and contains any combination of structural, dataflow, or behavioral descriptions used to describe the internal working of the entity.

For example, consider a dataflow level description of a two-input AND gate. This is shown in the right cavalcade of Figure 4.11, and the corresponding line numbers are in the left column for informational purposes only. The design has two inputs (A and B) and ane output (Z). The lawmaking has three main parts:

Figure 4.11. Two-input AND gate description in VHDL

1.

Elevation office identifies the reference libraries to utilize inside the design

2.

Eye part identifies the pattern entity

iii.

Bottom part identifies the design architecture.

Comments in VHDL start with –. Lines 1 to 3 and 22 to 24 are comments at the kickoff and ending of the file (with a .vhd extension) containing the VHDL code.

•

Line five identifies the reference library to employ in this design (IEEE), and line 6 identifies and the part(s) of the library to use.

•

Lines eight to 12 declare the entity (with a proper name And_Gate) and the I/O connections (ports).

•

Lines 14 to 20 identify the architecture body, using the built-in logical and operator to define the operation of the blueprint within the compages.

•

Lines 4, 7, thirteen, fifteen, 17, 19, and 21 are blank lines to assist code readability.

An example test bench used to simulate the design is shown in Figure iv.12. The structure of the test bench is the same as for a circuit design, except that at that place are no inputs to or outputs from the test demote. The stimulus to apply to the excursion is defined within the test bench, and an instance of the circuit is placed within the test demote.

Figure 4.12. VHDL test demote for a ii-input AND gate description

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Circuit Modeling with Hardware Description Languages

In Height-Downward Digital VLSI Blueprint, 2015

iv.8.vii Coding guidelines

Third-party HDL code tin can be very painful to prefer and adapt if its style significantly differs from that of other HDL components and from the practice of the system integrators. An early on book with advice on how to write reusable HDL lawmaking was [135], but most of information technology is part of good pattern practice anyway. While many companies and organisations have adult coding and reuse guidelines for internal usage, ESA was amongst the first to make theirs widely accessible [136]. A naming convention for VHDL signals adult by the author and his colleagues is to be introduced in department half-dozen.7. In 2008, NXP has published their reuse standards under the characterization CoReUse [137]. Unfortunately, an industry-wide consensus is nowhere in sight.

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An Engineering science Environment for Hardware/Software Co-Simulation

David Becker , ... Stephen G. Tell , in Readings in Hardware/Software Co-Design, 2002

four.three Communication through the Verilog simulator

The Verilog hardware description language does not contain any interprocess communication facilities. It does accept a Programming Language Interface (PLI) that allows user written C or C++ code to be chosen from within the simulation[S]. We used this PLI facility to add together extensions to the simulator then the remote software programs could brand a TCP connexion to the simulator program and communicate with modules within the simulation. The start strategy we used involved specialized extensions for each co-simulation link. From that experience, we devised a general machinery that we experience is much easier to employ and draw.

The Verilog PLI facility assembly a user written subroutine with a Verilog task name. Invoking a user written chore in a Verilog program will crusade the simulation to telephone call the C++ function associated with that task proper noun. These functions are called under several circumstances. One possible configuration is to take the C++ function chosen whenever an argument to the Verilog task changes during simulation. Our first communication mechanism is based on this form of user part.

Two tasks were added to Verilog in the original solution: $sparc () and $band (). In the processor module, the pipeline executes NOP instructions unless the $spare () task signals through one of its arguments that the firmware requests execution of an LD, ST or RETT instruction. The Verilog module and $ssparc () communicate through a modest set of arguments, shown in Figure 4.

Figure four. Parameters passed to $sparc() past the cy7c611 () module.

Since the clock betoken is an argument, the C++ code associated with $spare () is called every clock bike. During each cycle the C++ code tin read and write the signal lines connected to information technology. On the initial wheel, it connects to the firmware process. When the reset signal is negated, a RESET bulletin is sent to the firmware process. On subsequent cycles, $sparc () checks for messages from the firmware process. The C++ lawmaking sets the $sparc () parameters to the didactics, address and information equally needed for that wheel. When the bike completes, $spare () is signalled with the results and so the C++ code can send a message dorsum to the firmware process. With the exception of the clock, these arguments do not represent any actual electrical signals, but are only a advice mechanism between the simulation module and C++ code.

The ring port simulation module functions in a similar fashion, associating $ring () with its C++ code. When $ring () is initially called, information technology creates a socket to which the monitoring plan can connect. Thereafter, on every clock wheel $ring () checks to meet if the command program has connected. Once connected, $band () relays letters between the simulated hardware port and the monitor program. When a WRITE message is received, it begins clocking the message into the port one word per cycle. When the hardware sends data to the port, $ring () stores information technology until the end of message indicate is asserted. At the end of the message, a READ message is sent over the socket to the monitoring process.

A custom addition to the Verilog simulator for each link had several problems. Ane was writing a third piece of custom code for each link and some other was the difficulty of modifying the simulator program. Further, the original C++ code performed some link-specific operations on the messages which were easily moved into Verilog or deemed unnecessary. Verilog is more suited for checking signals each clock bike and sending acknowledgment signals. C++ is suited for making the networking system calls, and then our new implementation extends Verilog with tasks only for generalized interprocess communication (IPC). The form of job/user function clan used with these tasks arranges for the C++ role to be called every time its chore is invoked during simulation.

The IPC facility added to Verilog allows modules to create TCP connections to remote Unix programs during the simulation. The $makeserver () chore creates a Unix socket at the specified TCP port on the machine running the simulation. The software component of the co-simulation can connect to the simulation past using the IP accost of the reckoner running Verilog and the TCP port number beingness served.

The $send () and $recv () tasks communicate with programs that connect to the TCP ports set upwardly by $makeserver (). The transport task takes a variable number of arguments, all of which are put into a parcel and sent to the remote program. If the server is not connected to a remote program, the $transport () call is ignored. Each call of the $recv () task checks for an arriving message. If a message has arrived, the arguments to $recv () are filled with the message data. When no remote program is connected or no incoming data is waiting, $recv () sets its commencement data parameter, conventionally used for a message type identifier, to zero and ignores the other parameters.

Some software components need to know the country of the simulation when they connect. The $connect () task returns true if the associated server is connected to a remote plan. Start-up messages can exist sent when the connection is established. The $disconnect () task terminates the current connection of the server and tin can be preceded by shutdown messages. Just ane remote program tin connect to a server at a time. Later a server disconnects, a new connection can be polled for with the connect call. This mechanism is used past our processor co-simulation to start the firmware process when the processor reset signal is negated.

The software developed for the co-simulation environment includes Verilog simulator extensions, Verilog simulation modules and modified versions of the hardware interface functions. The Verilog modules for the processor and ring port were moderately complex, requiring about 700 lines of commented code for behavioral simulation. Only a small portion of this code is concerned with interprocess communications; the rest would have to be written for other simulation strategies equally well. The IPC tasks added to the interpreter were written in about 200 lines of commented C++ lawmaking and the simulation interface functions for the software components required 300 lines of commented C++ lawmaking.

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Functional verification

Hung-Pivot (Charles) Wen , ... Kwang-Ting (Tim) Cheng , in Electronic Design Automation, 2009

ix.3.3.1 Line coverage (a.grand.a. statement coverage)

This metric takes the syntactical HDL implementation and counts the number of lines exercised during the simulation run. The line coverage is defined as:

$\text{Line}\text{Coverage}=\frac{\#\text{of}\text{exercised}\text{lines}\text{in}\text{HDL}}{\text{Full}\#\text{of}\text{lines}\text{in}\text{HDL}}\times 100\%$

Consider the following Verilog HDL code in Box nine.1:

Box 9.i

i.

ever @(in or reset) begin

2.

out = in;

3.

if (reset)

4.

out = 0:

5.

en = 1;

6.

terminate

If the testbench exercises lines one, two, 3, 5, and half dozen, the line coverage would be five/vi = 83.three%. The line coverage is easy to comprehend, and the missed line explicitly indicates the absence of signal activities. One obvious drawback of line coverage is its lack of a clear connection betwixt the number of exercised lines and the correctness of design intent.

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"Traditional" Design Flows

Clive Max Maxfield , in FPGAs: Instant Admission, 2008

A Simple (early) HDL-based ASIC Menstruum

The key feature of HDL-based ASIC design flows is their use of logic synthesis technology, which began to appear on the market around the mid-1980s. These tools could accept an RTL representation of a pattern along with a gear up of timing constraints. In this case, the timing constraints were presented in a side-file containing statements along the lines of "the maximum filibuster from input X to output Y should exist no greater than N nanoseconds" (the bodily format would be a lilliputian drier and more boring).

The logic synthesis awarding automatically converted the RTL representation into a mixture of registers and Boolean equations, performed a multifariousness of minimizations and optimizations (including optimizing for area and timing), and then generated a gate-level netlist that would (or at least, should) meet the original timing constraints (Effigy 5-15).

Figure 5-xv. Uncomplicated HDL-based ASIC flow.

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